As semiconductor devices continue to advance and dimensions of the devices continue to shrink, accurately manufacturing the device dimensions becomes increasingly more important, particularly for 20 nm technology devices and beyond. Certain challenges arise in manufacturing such advanced devices, such as ensuring that drawn dimensions in the design stage result in desired dimensions after manufacturing. For certain devices (e.g., static random-access memory (SRAM), embedded random-access memory (eDRAM), and read-only memory (ROM)), precise control of transistor channel width is critical for both performance and obtaining functional yield targets. Further, differences between drawn transistor channel widths and manufactured, effective channel widths may be upwards of 25%, such as a 14 to 15 nm difference between drawn and effective channel widths for SRAM devices. Yet, there is currently no way to extract the change in transistor channel width between design and manufacturing that is cost effective and does not destroy the device, particularly for 20 nm technology devices and beyond.
A need, therefore, exists for a cost effective methodology and an apparatus for accurate extraction of transistor channel width.